Low Power Verification/Methodology Engineer Full Time

Preferred Qualifications Hands on experience on UVM methodology and System Verilog assertions Familiarity with advanced low power techniques and tools such as UPF, CLP and power aware DV Proficiency in Verilog/System Verilog coding, verification techniques, and scripting language, such as:
Perl, Python, Tcl, and Make etc. Good understanding of SoC architecture/micro-architecture. Strong debugging capabilities at simulation, including ability to design novel debug experiments.
Collaborate closely with cross-function team to research, design and implement performance and power management strategy for product roadmap Education
Requirements Preferred: Masters of Science degree in Computer Engineering, Computer Science, or Electrical Engineering, and/or prior industry experience.
Required: Bachelors of Science degree in Computer Engineering, Computer Science, or Electrical Engineering.
Preferred: Masters of Science degree in Computer Engineering, Computer Science, or Electrical Engineering, and/or prior industry experience.
Keywords Low Power verification, Verification, Emulation, EDA, UPF1.0, UPF2.0 OVM, UVM, Electronic Design Verification, VHDL, Verilog, Perl, Python, Tcl, C/C++,

Tagged as: computer science, design verification, eda tools, formal methods, perl, power management, python, system verilog, TCL, verilog, vhdl